1. Field of the Invention
The present invention relates to a delay locked circuit, and more particularly to an improved delay locked circuit which is capable of maintaining a locked state based on a phase difference between an input clock signal and an-internal signal.
2. Description of the Conventional Art
FIG. 1 illustrates a conventional delay locked circuit. The conventional delay circuit of FIG. 1 includes a phase detection unit 1 for comparing the phase of an input clock signal RCLK with the phase of an internal clock signal ICLK, a delay controller 2 for outputting two control signals Vp and Vn which determine the delay skew of the input clock signal RCLK in accordance with a result of the phase detection unit 1, and a variable delay unit 3 for outputting an internal clock signal ICLK by delaying the input clock signal RCLK based on two control signals Vp and Vn.
The phase detection unit 1 is a D flip-flop for receiving an input clock signal RCLK through an input terminal CLK and an internal clock signal ICLK through an input terminal D.
The operation of the conventional delay locked unit will now be explained with reference to FIGS. 2 through 5.
An input clock signal RCLK is externally inputted into a clock signal terminal CLK of the phase detection unit 1 and the variable delay unit 3, respectively. In the variable delay unit 3, the signal RCLK is delayed as much as one full period of is the signal RCLK based on the control signals Vp and Vn from the delay control unit 2. The delayed clock signal, output from variable delay unit 3, is known as an internal clock signal ICLK.
The phase detection unit 1 determines a logic state of the output signal in accordance with a logic state of the internal clock signal ICLK and a rising edge of the input clock signal RCLK.
When a low level input clock signal RCLK is input into the delay controller 2, the input clock signal RCLK is delayed for a predetermined time by two inverters I1 and I2, after which the transmission gate T1 is turned on. The internal clock signal ICLK is delayed by two inverters I4 and I5, is passed through the transmission gate T1, and is latched by the inverters I6 and I7.
When the level of the input clock signal RCLK is changed to a high level, the transmission gate T1 is turned off, and the transmission gate T3 is turned on. The internal clock signal ICLK latched by the inverters I6 and I7 passes through the transmission gate T3, is inverted by the inverter I8, and then is output to the output terminal Q. The signal is also inverted by the inverter I10 and is output to the output terminal QB.
When the internal clock signal ICLK has a high level state at a rising edge of the input clock signal RCLK, the logic state of the signal output from the output terminal Q becomes a high level, and the logic state of the signal output from the output terminal QB becomes a low level. The timing related to the signal is shown in FIG. 3A.
The operation of the delay controller 2 and the variable delay unit 3 will now be explained with particular reference to FIGS. 4 and 5.
The PMOS transistor P42 is turned off and the NMOS transistor N41 is turned on when the bias generator 41 of the delay controller 2 outputs a bias voltage, the enable signal PWON is a high state, the signal outputted from the output terminal Q of the detection unit 1 is a high level, and the signal outputted from the output terminal QB is a low level. While PMOS transistor P42 is turned off and the NMOS transistor N41 is turned on, the electric charge stored by capacitor C is discharged by the resistor R and the NMOS transistors N41, N42 and N43.
The level at the output terminal Vn is decreased, while the level at the output terminal Vp is increased. Therefore, the resistances of a plurality of PMOS transistors (P51,. P53, . . . , Pn) of the variable delay unit 3 are increased, and the resistances of a plurality of NMOS transistors (N51, N53 . . . , Nn) are increased.
The time for which the input clock signal RCLK passes through inverter I51 including transistors P52 and N52 and inverter I52 including transistor P54 and N54 is increased. When the input clock signal RCLK is at a rising edge, the phase difference between the input clock signal RCLK and the internal clock signal ICLK is decreased.
FIG. 3B illustrates a timing diagram of signals output from the terminals Q and QB when the phase of the internal clock ICLK is earlier than the phase of the input clock signal RCLK. If the logic states of the signals output from the output terminals Q and QB are opposite to the logic state shown in FIG. 3B, the delay controller 2 and the variable delay unit 3 are reversely operated.
Namely, the PMOS transistor P42 of the delay controller 2 is turned on, and the NMOS transistor N41 is turned off, causing capacitor C to be charged by the power voltage VDD. Therefore, the level of the output terminal V is increased, and the level of the output terminal V is decreased, causing the delay unit 3 to reduce a delay time of the input clock signal RCLK.
Moreover, based on the input clock signal RCLK, the conventional delay locked circuit determines whether the phase of the internal clock signal ICLK is earlier or later than the phase of the input clock signal RCLK. As a result of the judgement, if the phase of the internal clock signal ICLK is earlier than the phase of the input clock signal RCLK, the delay of the internal clock ICLK is extended. By contrast, if the phase of the internal clock signal ICLK is later than the phase of the input clock signal RCLK, the delay of the internal clock signal ICLK is shortened. For that reason, the conventional system operates in two modes.
In this system, if the phase of the internal clock signal ICLK is slightly earlier than the phase of the input clock signal RCLK, the phase of the internal clock signal ICLK becomes slower than the phase of the input clock signal ICLK in the next stage. The above-described two modes are therefore continuously operated.
Specifically, when the delay locked loop is clocked, the phase of the internal clock signal is always either earlier or later than the phase of the input clock signal RCLK. As shown in FIG. 3C, since there is always a predetermined time difference between the phases of two clock signals, an internal step jitter problem occurs, rendering it impossible to obtain an accurate locking operation using the conventional system.